Efficient space-time adaptive processing (stap) filter for global positioning system (gps) receivers

ABSTRACT

A system for efficiently filtering interfering signals in a front end of a GPS receiver is disclosed. Such interfering signals can emanate from friendly, as well as unfriendly, sources. One embodiment includes a GPS receiver with a space-time adaptive processing (STAP) filter. At least a portion of the interfering signals are removed by applying weights to the inputs. One embodiment adaptively calculates and applies the weights by Fourier Transform convolution and Fourier Transform correlation. The Fourier Transform can be computed via a Fast Fourier Transform (FFT). This approach advantageously reduces computational complexity to practical levels. Another embodiment utilizes redundancy in the covariance matrix to further reduce computational complexity. In another embodiment, an improved FFT and an improved Inverse FFT further reduce computational complexity and improve speed. Advantageously, embodiments can efficiently null a relatively large number of jammers at a relatively low cost and with relatively low operating power.

RELATED APPLICATIONS

This application is a continuation application of U.S. application Ser.No. 11/000,827, filed on Dec. 1, 2004, which is a divisional applicationof U.S. application Ser. No. 10/256,060, filed Sep. 26, 2002, now U.S.Pat. No. 6,952,460, which claims the benefit under 35 U.S.C. § 119(e) ofU.S. Provisional Application No. 60/325,373, filed Sep. 26, 2001, thedisclosures of which are hereby incorporated by reference herein.

This application is also related to application Ser. No. 11/000,861,filed Dec. 1, 2004, now U.S. Pat. No. 7,197,095; to application Ser. No.11/000,718, filed Dec. 1, 2004, and to application Ser. No. 11/866,925,filed Oct. 3, 2007, which is a continuation application of applicationSer. No. 11/000,718, the disclosures of which are hereby incorporated byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention is generally related to GPS receivers, and in particular,to acquisition and tracking of a pseudorandom noise (PN) signal in aGlobal Positioning System (GPS) receiver in a relatively noisyenvironment.

2. Description of the Related Art

The Global Positioning System (GPS) Operational Constellation nominallycomprises 24 earth-orbiting satellites. Each satellite radiates a spreadspectrum, pseudorandom noise (PN) signal indicating the satellite'sposition and time. A GPS receiver tuned to receive the signals from thesatellites can compute the distance to the satellites and calculate thereceiver's position, velocity, and time. The receiver calculates thedistance to a satellite by multiplying the propagation rate of thesatellite's radio signal, i.e., the speed of light, by the time it tookthe signal to travel from the satellite to the receiver.

Each satellite transmits two carrier signals referred to as L1 and L2.L1 operates at a frequency of 1.57542 GHz and L2 operates at a frequencyof 1.22760 GHz. Multiple binary codes induce phase modulation upon theL1 and L2 carrier signals. Each satellite in the GPS OperationalConstellation transmits a unique code over the L1 and L2 carriersignals. One of the phase-modulated signals is C/A Code (CoarseAcquisition Code). Presently, 32 codes are defined for the C/A Code. Asatellite's C/A Code phase modulates the L1 carrier over a 1.023 MHzbandwidth. The C/A Code is a repeating 1023 bit sequence. At 1023 bitsand 1.023 MHz, the C/A Code repeats every millisecond. The C/A Codeforms the basis for the Standard Positioning Service (SPS) used bycivilians.

Another phase-modulated signal is the P-Code (Precise Code). The P-Codeis similar to the C/A Code in that it is a PN sequence which phasemodulates a carrier signal. The P-Code modulates both the L1 and the L2signals at a rate of 10.23 MHz. In an Anti-Spoofing mode, the P-Code isencrypted to produce the Y-Code to restrict access to users with theencryption key. The P-Code forms the basis for the military's PrecisePositioning Service (PPS). It will be understood that additionalsignals, such as M-Code, can be added to existing carriers or toadditional carriers.

A GPS receiver preferably functions in a variety of environments. Bothfriendly and unfriendly environments can include interference. Forexample, jammers from “unfriendly” sources can intentionally causeinterference. Interference can also originate from “friendly” sources,such as radar transmitters and commercial television transmitters. Forexample, non-linearities in RF power amplifiers can create out-of-bandRF signals, which in turn cause RF interference to GPS receivers. In thepresence of interference, a GPS receiver can fail to acquire a GPSsignal quickly, if at all. This can lead to undesirable errors innavigation, guidance, tracking, etc.

One technique that has been used in radar receivers to filter outinterfering signals is space-time adaptive processing (STAP).Disadvantageously, conventional STAP techniques are computationally verycomplex and typically require the use of a very powerful computer tocompute in real time.

SUMMARY OF THE INVENTION

A system for efficiently filtering interfering signals in a front end ofa GPS receiver is disclosed. Such interfering signals can emanate fromfriendly, as well as unfriendly, sources. One embodiment includes a GPSreceiver with a space-time adaptive processing (STAP) filter. At least aportion of the interfering signals are removed by applying weights tothe inputs. One embodiment adaptively calculates and applies the weightsby Fourier Transform convolution and Fourier Transform correlation. Inone embodiment, the Fourier Transform is computed via a Fast FourierTransform (FFT). This approach advantageously reduces computationalcomplexity to practical levels. Another embodiment utilizes redundancyin the covariance matrix to further reduce computational complexity. Inanother embodiment, an improved FFT and an improved Inverse FFT furtherreduce computational complexity and improve speed. Advantageously,embodiments can efficiently null a relatively large number of jammers ata relatively low cost and with relatively low operating power.

One embodiment includes a method of filtering interference in a GPSreceiver, where the method includes: receiving digital input samplesfrom a plurality of antenna elements; computing Fourier Transforms ofthe digital input samples, wherein the Fourier Transforms of inputsamples of one antenna element are identifiably maintained from FourierTransforms of input samples of another antenna element; using FourierTransform correlation to compute a cross-power spectra for the antennaelements; computing an Inverse Fourier Transform of the cross-powerspectra; calculating a covariance matrix from the Inverse FourierTransform of the cross-power spectra; inverting the covariance matrix;multiplying the inverted covariance matrix with a steering vector togenerate weights; and applying the weights to the digital input samplesto filter the interference.

Another embodiment includes a GPS receiver adapted to filterinterference, where the GPS receiver includes: a plurality of inputcircuits configured to receive digital input samples from a plurality ofantenna elements; a plurality of first signal processors configured tocompute Fourier Transforms of the digital input samples, wherein theFourier Transforms of input samples of one antenna element areidentifiably maintained from the Fourier Transforms of input samples ofanother antenna element; a second signal processor configured to computea cross-power spectra for the antenna elements from the FourierTransforms; a third signal processor configured to compute an InverseFourier Transform of the cross-power spectra; a fourth signal processoris configured to calculate a covariance matrix from the Inverse FourierTransform of the cross-power spectra; a fifth signal processorconfigured to invert the covariance matrix to an inverted covariancematrix; a sixth signal processor configured to multiply the invertedcovariance matrix with a steering vector to generate weights; and aseventh signal processor configured to applying the weights to thedigital input samples to filter the interference.

One embodiment includes a method of calculating a sub-matrix of acovariance matrix for a GPS space-time adaptive processing (STAP)filter, where the method includes: calculating at least one row of thesub-matrix; and copying at least one value from the calculated row,where the copied value is loaded to a position in the sub-matrix that isdisplaced in time from the calculated value.

One embodiment includes a signal processor adapted to calculate asub-matrix of a covariance matrix for a GPS space-time adaptiveprocessing (STAP) filter, where the signal processor includes: means forcalculating at least one row of the sub-matrix of the covariance matrixfor the GPS STAP filter; and means for copying at least one value fromthe calculated row, where the copied value is loaded to a position inthe sub-matrix that is displaced in time from the calculated value.

One embodiment includes a method of reusing data in a GPS space-timeadaptive processing (STAP) filter, where the method includes:calculating a Fourier Transform of input samples for an antenna element;using the calculated Fourier Transform to compute Fourier Transformcorrelation; and using the same calculated Fourier Transform to computeFourier Transform convolution to reuse the data.

One embodiment includes a GPS space-time adaptive processing (STAP)filter, where the STAP filter includes: a plurality of Fourier Transformprocessors configured to transform input samples from time domain tofrequency domain; a plurality of Fourier Transform correlation circuitscoupled to the Fourier Transform processors, where a Fourier Transformcorrelation circuit is configured to combine input samples with weightsin frequency domain such that a presence of an undesired signal in theinput samples is reduced; and a plurality of Fourier Transformconvolution circuits coupled to the Fourier Transform processors, wherea Fourier Transform convolution is configured to at least computecross-power spectra between multiple antenna elements.

One embodiment includes a method of inverting a covariance matrix in aGPS space-time adaptive processing (STAP) filter, where the methodincludes: performing triangular factorization on the covariance matrix;and performing substitution to invert the covariance matrix.

One embodiment includes a method of integrating correlation data in aGPS space-time adaptive processing (STAP) filter, where the methodincludes: receiving a plurality of cross-power spectra computations,where the cross-power spectra computations are related to an antennaelement in a multiple-element antenna array; and integrating theplurality of cross-power spectra computations with lossy integration.

One embodiment includes a signal processor in a GPS space-time adaptiveprocessing (STAP) filter, where the signal processor includes: amultiplier in a Fourier Transform correlation circuit, where themultiplier computes at least a cross-power spectra of one antenna arrayand another; and a memory coupled to the multiplier, where the memory isconfigured to calculate lossy integration of values from the multiplier.

One embodiment includes a method of computing a Fast Fourier Transform(FFT), where the method includes: receiving input samples in naturalorder; providing the input samples directly to an FFT pipeline without adelay stage that implements filling of a constant, wherein the directloading to the FFT pipeline includes the constant loading; andprocessing the input samples through the FFT pipeline.

One embodiment includes an input stage for a pipelined circuit thatcomputes a Fourier Transform, where the input stage includes: amultiplier configured to multiply input samples with twiddle factors; afirst delay stage coupled to an output of the multiplier; a switchcoupled to an input of the multiplier and to an output of the firstdelay stage, where the switch is configured to provide a straightconnection in a first state and a cross connection in a second state; asecond delay stage coupled to an output of the switch; and a butterflystage coupled to the switch and to the second delay stage, where thebutterfly stage is configured to couple to another stage of thepipelined circuit for processing of the Fourier Transform.

One embodiment includes a method of computing an Inverse Fast FourierTransform (IFFT) with Lap and Add, where the method includes: receivingvalues from frequency bins in reverse binary order; computing at leastpart of the IFFT in a radix-2 pipeline from the received values;delaying a difference output of an output butterfly to generate adelayed difference output; and summing a sum output of the outputbutterfly with the delayed difference output to provide a natural orderoutput IFFT with Lap and Add output.

One embodiment includes a pipelined circuit for computing an InverseFourier Transform, where the pipelined circuit includes: a plurality ofbutterfly stages, where the butterfly stages are configured to computesum and differences of their inputs, wherein a first butterfly stage isconfigured to receive an input in reverse binary order; a plurality ofmultipliers coupled to difference outputs of the butterfly stages, wherethe multipliers are configured to multiply the difference outputs withtwiddle factors; a plurality of first delays circuits coupled to themultipliers; a plurality of switches coupled to the sum outputs of thebutterfly stages and to the delays, where the switches are configured toswitch between straight and cross connections; a plurality of seconddelays circuits coupled to outputs of the switches; wherein a seconddelay circuit is matched in delay to a corresponding first delaycircuit; a third delay circuit coupled to a difference output of a lastof the butterfly stages, wherein the third delay circuit is configuredto have twice the delay of the second delay circuit that is coupled tothe last of the butterfly stages; and a summing circuit coupled to a sumoutput of the last of the butterfly stages and to an output of the thirddelay circuit such that the summing circuit laps and adds the sum outputof the last of the butterfly stages with the output third delay circuit,where an output of the summing circuit is an Inverse Fourier Transformin natural order of the inputs.

One embodiment includes a method of enhancing tracking in a carrierphase locked loop of a GPS receiver, where the method includes:calculating an approximate phase shift induced by application of theweights that are adaptively applied to an input baseband signal by aspace-time adaptive processing (STAP) filter; and steering the carrierphase locked loop with the calculated phase shift to assist the carrierphase locked loop to maintain phase lock with the phase shifted basebandsignal.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the invention will now be described withreference to the drawings summarized below. These drawings and theassociated description are provided to illustrate preferred embodimentsof the invention and are not intended to limit the scope of theinvention.

FIG. 1A generally illustrates conventional space-time adaptiveprocessing.

FIG. 1B generally illustrates space-time adaptive processing (STAP)according to one embodiment.

FIG. 1C illustrates a block diagram of a front end of a GPS receiverwith a space-time adaptive processing (STAP) filter.

FIG. 1D illustrates a block diagram of a portion of a GPS STAP filter.

FIG. 2A illustrates 6 unique sub-matrices in a STAP covariance matrixfor a 3-element array.

FIG. 2B illustrates 28 unique sub-matrices in a STAP covariance matrixfor a 7-element array.

FIG. 3 illustrates mapping into a covariance matrix.

FIGS. 4A and 4B illustrate mapping into a covariance matrix according toone embodiment.

FIG. 5 illustrates sample data in a covariance matrix.

FIG. 6 illustrates one embodiment of a GPS STAP Filter.

FIG. 7 illustrates one embodiment of a Fast Fourier Transform (FFT)processor.

FIG. 8 illustrates one embodiment of an Inverse FFT processor with Lapand Add.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Although this invention will be described in terms of certain preferredembodiments, other embodiments that are apparent to those of ordinaryskill in the art, including embodiments that do not provide all of thebenefits and features set forth herein, are also within the scope ofthis invention. Accordingly, the scope of the invention is defined onlyby reference to the appended claims.

Space-time adaptive processing (STAP) is a powerful two-dimensionalfiltering technique that adaptively calculates a weight vector inresponse to received signals. Disadvantageously, the weight vector isdifficult to compute using conventional techniques. Embodimentsadvantageously compute the weight vector with efficiency, therebypermitting STAP filtering techniques to be applied in a GPS receiver.

FIG. 1A generally illustrates conventional space-time adaptiveprocessing. In a first step 20, the input samples are received. Acovariance matrix is calculated in a second step 22. The calculation ofa covariance matrix by conventional techniques is computationallycomplex. In a third step 24, the covariance matrix is inverted by amatrix inversion technique. In a fourth step 26, the inverted covariancematrix is multiplied by a steering vector to generate weights. In afifth step 28, the weights are applied to the input samples via a finiteimpulse response (FIR) filter.

FIG. 1B generally illustrates space-time adaptive processing (STAP)according to one embodiment. It will be understood that the process canbe configured to run continuously, such that the recited steps can be inoperation continuously, and the steps can be operated in parallel witheach other. The process will now be generally described with respect todata flow within the process. In a first step 50, the input samples fromone or more antennas of a GPS system are received. The number ofantennas n (or antenna elements) accessed by the STAP filtering can berelated to the number of broadband interference sources that can benulled by the STAP filtering. Typically, the number of broadband jammersthat can be nulled by STAP filtering corresponds to n−1. The number ofnarrow-band interference sources that can be nulled is typically relatedto the number of frequency bins calculated with Fourier Transforms. Theprocess advances to a second step 52.

In the second step 52, Fast Fourier Transforms (FFTs) of the inputsignals are computed. Although the GPS STAP filter techniques aredescribed generally in the context of Fast Fourier Transforms (FFTs), itwill be apparent to one of ordinary skill in the art that othertechniques, such as Discrete Fourier Transform (DFT) and InverseDiscrete Fourier Transform (IDFT) techniques are also applicable. Inaddition, it will be understood by one of ordinary skill in the art thatthere are many different variations of Fourier Transform computationtechniques that are called “Fast Fourier Transforms.”

Where more than one antenna element is provided in a system, the inputsamples from each antenna element will typically be individuallytransformed via an FFT. It will be understood that the DFT can becomputed instead of the FFT, but that the DFT can be more complex tocalculate, particularly when the number of frequency bin calculations isrelatively large. In addition, it will be understood that the GPS STAPfilter techniques described herein are applicable to GPS signals, whichmay be received for relatively long periods of time. To transform arelatively long input sequence, the input sequence can be broken up intorelatively small pieces, which are individually transformed and thenlater combined. These techniques will be described in greater detaillater in connection with FIG. 8. The process advances from the secondstep 52 to a third step 54.

In the third step 54, the process computes the cross-power spectra,preferably for each antenna, via FFT correlation techniques. Computationof the cross-power spectra is described in greater detail later inconnection with FIG. 1D. The process advances from the third step 54 toa fourth step 56. In the fourth step 56, inverse FFTs (IFFTs) for thecross-power spectra are computed, and the process advances to a fifthstep 58. In the fifth step 58, the results of the IFFTs are loaded intoa matrix to form the covariance matrix. Advantageously, the steps withina dashed box 60 calculate a covariance matrix with relatively lesscomputing power than is typically needed for the same results usingconventional techniques. The process advances from the fifth step 58 toa sixth step 62.

In the sixth step 62, the process inverts the covariance matrix. Avariety of matrix inversion techniques can be used to invert thecovariance matrix. The process advances from the sixth step 62 to aseventh step 64. In the seventh step 64, the process multiplies theinverted covariance matrix with a steering vector. This generates theweights that will be applied to the input samples. The weights canadjust the amplitude and the phase of the input samples. In oneembodiment, the weights are repeatedly updated such that the processadapts to changing interference conditions. The weights generated fromthe inverted covariance matrix, as multiplied by the steering vector,serve to reduce the power received. In one typical environment, thesignal from a jammer can be 40-50 dB above the noise. The GPS signal islargely unaffected by the weights, as a GPS signal is typically about 30dB below the noise and undetected by the STAP filtering.

A variety of techniques can be used to apply the weights, including theFIR filter techniques described earlier in connection with FIG. 1A. Inone embodiment, the process uses computationally efficient FFTconvolution techniques to apply the weights, as described in an eighthstep 66 and a ninth step 68. In another embodiment, the process uses FIRfiltering techniques to apply the weights to the input samples.

In the eighth step 66, the process computes an FFT of the weights, andthe process applies the weights to the input samples with FFTconvolution. The process advances from the eighth step 66 to the ninthstep 68. In the ninth step 68, the process computes an IFFT of the FFTconvolution, thereby generating a filtered baseband signal that isprovided as an input to further baseband processing circuits, such asquadrature demodulation circuits, acquisition circuits, and the like.Such STAP techniques can efficiently filter interfering signal in a GPSreceiver.

In a GPS receiver, the GPS signals from the satellites are typicallyreceived by one or more antenna and amplified by low-noise amplifiers.The received signals are then typically downconverted to baseband with aquadrature demodulator. The baseband in-phase (I) and quadrature-phase(Q) signals are then converted to digital by analog-to-digitalconverters, and are provided to acquisition circuits, which “acquire” aparticular satellite by matching a code received by the GPS receiver toa code defined for the satellite. FIG. 1C is a system diagram thatillustrates where space-time adaptive processing can advantageously belocated in the data flow of a front-end portion of a GPS receiver. Forclarity, FIG. 1C does not include small details, such as low-passfilters. The illustrated portion of the GPS receiver includes an antenna102, a low noise amplifier (LNA) 104, a mixer 108, an analog-to-digitalconverter 110, a space-time adaptive processing (STAP) filter 112, andfurther baseband processing 114.

In the illustrated portion of the GPS receiver, the RF GPS signal isreceived by the antenna 102. It will be understood that the antenna 102can include an array of antennas. The antenna 102 is coupled to the LNA104. Where more than one antenna is used, each can be coupled to anindividual low noise amplifier. The output of the LNA 104 is mixed witha local oscillator signal 106 by the mixer 108 to provide an analogbaseband signal. It will be understood by one of ordinary skill in theart that the output of the mixer is filtered by a low-pass filter. Inaddition, it will be understood that the analog baseband signal cancorrespond to an intermediate frequency, and can be furtherdownconverted by another process, such as a quadrature demodulationprocess in the digital domain.

The output of the mixer 108 is provided as an input to theanalog-to-digital converter 110, which generates a digital basebandsignal. In one embodiment adapted to P(Y) Code, the analog-to-digitalconverter is configured to sample the output of the mixer 108 at a23.516 MHz rate. The digital baseband signal is provided as an input tothe STAP filter 112. It will be understood that where there is more thanthe antenna 102, the LNA 104, and the mixer 108 correspond to multipleantennas, low noise amplifiers, and mixers, the analog-to-digitalconverter 110 will also correspond to multiple analog-to-digitalconverters. The STAP filter 112 advantageously at least partiallycompensates for interference from one or more interfering signals. Oneembodiment of the STAP filter 112 is described in greater detail laterin connection with FIGS. 1D to 8.

The output of the STAP filter 112 is provided as an input to thebaseband processing 114, which can further include quadraturedemodulation circuits, acquisition circuits, carrier tracking loops,etc. In one embodiment, the acquisition circuits correspond to a fastacquisition front-end. One example of such a fast acquisition front-endis described in U.S. Pat. No. 6,452,961 to Van Wechel, entitledMASSIVELY PARALLELED SEQUENTIAL TEST ALGORITHM, the entirety of which ishereby incorporated by reference herein. The signal can then be furtherprocessed downstream by circuits that track the carrier phase for thesatellite, etc.

Disadvantageously, conventional techniques to calculate the weightvector used in the STAP filter 112 are very computationally complex. Thecomplexity of the computations increases dramatically with the number ofantennas or the number of antenna elements in a multiple-element array.To calculate the weight vectors, the input signal is sampled, and acovariance matrix is computed by cross-correlating multiple taps of FIRfilters for all the elements of an array of antennas. The covariancematrix is then inverted and multiplied by a steering vector to producethe set of weight vectors. The weight vectors are applied to the inputsignal via a Finite Impulse Response (FIR) filter. The process iscontinually repeated to adaptively recompute new weights for the inputsignal that will eliminate or at least reduce interference. However,even the calculation of the covariance matrix alone is a formidablecomputing task. These conventional STAP filtering techniques requirerelatively powerful processing power, such as the processing poweravailable in a supercomputer. The required processing power for STAPfiltering is not typically available in a GPS receiver. Whenconventional STAP filtering techniques are approximated or simplified toreduce the computational complexity such that the resulting sub-optimalSTAP filtering can be implemented with available processing power, thefiltering of the interference is far less than optimal. For example, oneconventional system with FFT processing in a STAP filtering applicationdoes not exploit space-time correlation for wideband jammers.

One embodiment provides full STAP filtering that is computationally lesscomplex than conventional STAP filtering techniques and canadvantageously be implemented with relatively less powerful computingresources. In one embodiment, the STAP filtering techniques are computedin a more efficient manner than conventional STAP filtering techniques.This permits full STAP filtering techniques to be used even wherepowerful computing resources are not available. Although the benefits ofcomputationally less complex STAP filtering techniques will be apparentto systems with one or with relatively few antenna or antenna elements,the computational savings become progressively more dramatic as thenumber of antenna or antenna elements increases. The disclosed STAPfiltering techniques are sufficiently efficient to permit one embodimentto be implemented in a field programmable gate array (FPGA). However, itwill be understood by one of ordinary skill in the art that thedisclosed techniques can also be combined with sub-optimal STAPfiltering techniques.

FIG. 1D illustrates a block diagram of an upstream portion of a STAPfilter 118 according to one embodiment. The upstream portion of the STAPfilter 118 shown in FIG. 1D efficiently supports the computation of thecovariance matrix with Fast Fourier Transform (FFT) convolution andcorrelation techniques. In one embodiment, the illustrated upstreamportion of the STAP filter 118 is implemented in hardware, such as in afield programmable gate array (FPGA), an application specific integratedcircuit (ASIC), programmable logic device, and the like. Other portionsof the STAP filter can be implemented in firmware or in software that isexecuted by a microprocessor or a digital signal processor (DSP), andthe like. It will be understood that the STAP filter can be partitionedinto hardware and software in a different manner than that illustrated,and it will also be understood that alternate embodiments include thosethat are implemented entirely in hardware or in software. While theillustrated embodiment is described in the context of an FFT, one ofordinary skill in the art will appreciate that Discrete FourierTransform (DFT) techniques are also applicable.

The illustrated STAP filtering techniques can be used with one or moreantennas. It will be understood that the number of antenna or antennaelements can vary in a broad range, and that the STAP filterconfiguration shown in FIG. 1D. In the illustrated embodiment of FIG.1D, the STAP filter is shown in a configuration suitable for a 3-elementantenna array. It will be understood by one of ordinary skill in the artthat the STAP filter can be used for 2 to n number of antenna elementsor to different polarization ports, e.g., right-hand circularpolarization (RHCP) and left-hand circular polarization (LHCP), and thatthe description of the 3-element configuration corresponds to oneexample. As used herein, the term “antenna element” covers both antennaelements and polarization ports. The digital baseband signals from theanalog-to-digital converters are provided as inputs to Fast FourierTransform (FFT) processors. For example, an output of theanalog-to-digital converter 110 is provided as an input to a first inputFFT processor 120. For clarity, the LNA 104 and the mixer 108 from FIG.1C are not reproduced in FIG. 1D.

The time-domain samples of the digital baseband signals are loaded intoFFT memories. In one embodiment, at least half of the memory space inthe FFT memories is filled with zeroes to prevent circular correlationsfrom being computed. The first input FFT processor 120 transforms thetime-domain samples of the digital baseband signal from theanalog-to-digital converter 110 from time domain to frequency domain.The number of frequency bins can correspond to a very broad range. Inone embodiment, the first input FFT processor 120 computes 64 frequencybins. In another embodiment, 16 points are computed. A second input FFTprocessor 122 and a third input FFT processor 124 transform thetime-domain samples from the digital baseband signals of theirrespective analog-to-digital converters. It will be understood by one ofordinary skill in the art that the signal processing for the otherantenna or other antenna elements can be processed in the same manner asthe signal processing for the first antenna. A variety of FFTconfigurations can be used for the input FFT processors. One particularembodiment of an input FFT processor that can advantageously be usedwith the STAP filter is described in greater detail later in connectionwith FIG. 7.

The output of the first input FFT processor 120 is advantageouslyprovided to both a first multiplier 126 and to an FFT Correlationcircuit 128. Use of the same FFT computation for both convolution andcorrelation enhances efficiency. In another embodiment, a separate FFTprocessor is used for convolution and for correlation. The firstmultiplier 126 performs a portion of the FFT convolution (or weightingor adding) by multiplying the frequency-domain representation orfrequency bins of the input signal by transformed weight vectors toreduce or remove interfering signals. The data flow path with the firstmultiplier 126 forms part of the beamforming and time-domain STAPfiltering, as will be explained in greater detail later with respect toFIG. 1D and also later in FIG. 6.

The illustrated FFT Correlation circuit 128 performs FFT Correlation for3 antenna elements. The FFT Correlation circuit 128 includes a firstmemory buffer 130 and a second memory buffer 132. The outputs of theinput FFT processors are provided as inputs to the first memory buffer130 and to the second memory buffer 132 of the FFT Correlation circuit128. The FFT Correlation circuit 128 is configured such that thecontents of the first memory buffer 130 and the second memory buffer 132are staggered or delayed by one FFT computation, i.e., the contents ofthe second memory buffer 132 are delayed by one FFT computation from thecontents of the first memory buffer 130. In one embodiment, the firstmemory buffer 130 and the second memory buffer 132 are implemented withdistributed random access memory (RAM).

A multiplexer 134 controlled by a multiplexer controller 136 selectsoutputs of the first memory buffer 130 and the second memory buffer 132such that the cross-power spectra between various antenna elements canbe computed. In one embodiment, all combinations of cross-power spectrafor the various element FFTs are computed. To compute the cross-powerspectra between two antenna elements, an FFT from a first antennaelement is multiplied with a delayed (prior computation) and conjugatedFFT of a second antenna element.

For example, with respect to the first antenna, the multiplexercontroller 136 selects between the first memory buffer 130 and thesecond memory buffer 132 to provide a first FFT correlator 138 with thedata needed to compute the cross-power spectra between the first antennaand the other antennas. The data corresponding to the FFT from the firstantenna for the current data, which in one embodiment corresponds to themost recent FFT computation, is retrieved from the first memory buffer130 by the multiplexer 134 and is provided to a multiplier 140 of thefirst FFT correlator 138. The multiplexer controller 136 furthercontrols the multiplexer 134 such that the data from an FFT computationfor the second antenna that is prior to the current data is provided asan input to a complex conjugation circuit 142.

The complex conjugation circuit 142 takes the complex conjugate of theprior FFT computation and provides it as an input to the multiplier 140.An output of the multiplier 140 is provided as an input to anintegration memory 144. The integration effectively averages multiplesamples of the cross-power spectra computations and improves the signalto noise ratio of the computed cross-power spectra. A variety ofintegration techniques can be used, including integrate and dumptechniques and lossy integration techniques.

With integrate and dump techniques, the integration memory 144integrates the cross-power spectra over a period of time. This period oftime is known as the integration period. In one embodiment, theintegration period is about 2 mS. In another embodiment, the integrationperiod is about 1 mS. The integration period can be varied in a verybroad range. For example, an integration period within a range betweenabout 0.5 mS to about 50 mS can be used. In another embodiment, theintegration period is in a range between about 1 mS to about 20 mS. Thelower limit for the integration period is determined by the point atwhich the covariance matrix remains solvable. In addition, it should benoted that the available processing power can place a practical limit onthe integration period.

However, integrate and dump techniques can perform relatively poorly inthe presence of “blinking jammers,” which broadcast interfering signalsin relatively short pulses. Integrate and dump techniques performparticularly poorly when the pulse rate of the blinking jammer matcheswith the integration period. Although the effects of blinking jammerscan be mitigated by changing or increasing the integration period, anincrease in the integration period can disadvantageously slow theresponse of the GPS STAP filter to interfering signals. In anotherembodiment, lossy integration techniques are used to mitigate againstblinking jammers.

Lossy integration techniques perform well in the presence of blinkingjammers. Lossy Integration differs from conventional integration. In aconventional integrator, such as an integrate and dump circuit, samplesof data are accumulated over the integration period, the accumulateddata is “dumped” at the end of the integration period, and the integrateand dump circuit is reset to perform another integration for the nextintegration period.

With lossy integration, the results of the integration are not dumped. Aportion of the integration results from prior periods is maintained inthe integrated sum, but gradually diminishes over time. One example oflossy integration is expressed in Equation 1, where I indicates thevalue of the lossy integrated sum, and x corresponds to the value thatis integrated. It will be understood that the values that are integratedare complex numbers.I _(new) =y·I _(old) +x(1−y)  (Eq. 1)

In Equation 1, y is a fraction. In one embodiment, y is a fraction witha denominator corresponding to a multiple of 2, which eases computationby permitting divisions to be implemented with bit shifts. For example,in one embodiment, the value of y corresponds to 63/64 and the value of(1−y) is 1/64. It will be understood that the value of y can vary in avery broad range.

In one embodiment, the output of the multiplier 140 is provided in a28-bit wide data path. The multiplexer controller 136 further selectsprior FFT computations from the other antenna elements, which aremultiplied by the multiplier 140 and integrated in the integrationmemory 144. The output Y1 146 of the integration memory 144 includes thecross-power spectra between a present FFT (channel 1 or antenna element1) and a present FFT (channel 2 or antenna element 2), where presentcorresponds to the recent FFT computation as retrieved from the firstmemory buffer 130. In one embodiment, the integration memory 144 is a64-bit by 1920 memory device. In one embodiment, the integration memory144 stores 64 frequency bins for at least each of the uniquecombinations for the covariance matrix. It will be understood that thenumber of frequency bins in the integration memory 144 can vary in avery broad range, but that the number of frequency bins is typically thesame as the number of frequency bins in the first input FFT processor120. Further details of one computation of the covariance matrix aredescribed later in connection with FIGS. 4A and 4B. In one example, a3-element antenna array has 6 unique combinations, and the integrationmemory 144 stores 64×6 or 64 frequency bins by the 6 uniquecombinations. In another example, with a 7-element antenna array, the7-element antenna array has 28 unique combinations, and the integrationmemory 144 stores 64×28 combinations. In one embodiment, furthercomputations needed to generate a covariance method are performed insoftware.

A second FFT Correlator 148 and a third FFT Correlator 150 compute thecross-power spectra between a present FFT (channel 1 or antenna element1) and prior FFT (channel 2 or antenna element 2) and between a priorFFT (channel 1 or antenna element 1) and present FFT (channel 2 orantenna element 2), where prior corresponds to the prior FFT computationas retrieved from the second memory buffer 132. The outputs of thesecond FFT Correlator 148 and the third FFT Correlator 150 arerepresented in FIG. 1D by the output Y2 152 and the output Y3 154,respectively. In one embodiment, the FFT Correlation circuit 128 isconfigured such that the first FFT Correlator 138, the second FFTCorrelator 148, and the third FFT Correlator 150 advantageously sharethe first memory buffer 130, the second memory buffer 132, and themultiplexer 134.

In one embodiment, the output Y1 146 is provided in a 32-bit wide datapath. In one embodiment, the output Y1 146 is read by a softwareprocess, which computes the covariance matrix from the cross-powerspectra data. Further details of the covariance matrix will be describedlater in connection with FIGS. 3 to 5. The cross-power spectra data fromthe various antenna elements are processed by an inverse FFT (IFFT),summed, and arranged in a covariance matrix. The covariance matrix isthen inverted, multiplied by a steering vector, and transformed to thefrequency domain by an FFT process, and the transformed result isprovided as a weight vector to the first multiplier 126.

The first multiplier 126 performs a portion of the FFT convolution (orweighting or adding) for the first antenna by multiplying thefrequency-domain representation or frequency bins of the input signal bytransformed weight vectors to reduce or remove interfering signals. Theoutput of the first multiplier 126 is combined with the outputs of asecond multiplier 160 and a third multiplier 162 by a beamformingsumming circuit 164. The output of the beamforming summing circuit 164is provided as an input to an Inverse Fast Fourier Transform (IFFT)processor 166, which converts the FFT convolution back to time-domain.The output of the IFFT processor 166 is provided as an input to a Lapand Add circuit 168. Another name for a Lap and Add technique is Overlapand Add. The Lap and Add circuit 168 recombines data that was broken upinto smaller pieces for ease of computation. Other techniques, such asselect-save techniques, can also be used. The output of the Lap and Addcircuit 168 is provided as an input to an interpolation circuit 170. Inone embodiment, the interpolation circuit 170 interpolates oroversamples the output of the Lap and Add circuit 168 by a factor offour. It will be understood that other oversampling rates, such as by 2,by 8, and the like can also be used.

FIG. 2A and FIG. 2B illustrate STAP covariance matrices for a 3-elementantenna array and for a 7-element antenna array, respectively. Theantenna elements are indicated along the rows and the columns of thematrices. As illustrated in FIGS. 2A and 2B, the size of the covariancematrix and the number of unique sub-matrices within a STAP covariancematrix, depends on the number of elements in the antenna array. Acovariance matrix is also known as a variance-covariance matrix. Asillustrated in FIG. 2A, a 3×3 covariance matrix for a 3-element antennaarray has 6 unique combinations. As illustrated in FIG. 2B, a 7×7covariance matrix for a 7-element array has 28 unique combinations.These combinations are sub-matrices in themselves. It will be understoodthat not all of the entries in a covariance matrix are unique becausethe covariance of A and B is the complex conjugate of the covariance ofB and A. Accordingly, a sub-matrix of the covariance at 2×1 is thecomplex conjugate of the sub-matrix of the covariance at 1×2, and bothneed not be computed (apart from the computationally simple task ofchanging the sign of the imaginary part of a number for complexconjugation).

FIG. 3 illustrates a STAP covariance matrix 300 for a 3-element antennaarray with conventional calculations for the sub-matrices. It will beunderstood that the number of antenna elements can vary in a very broadrange, and that the 3-element antenna array described in connection withFIGS. 3, 4A, and 4B is one example. The 3-element STAP covariance matrixincludes nine sub-matrices. The sub-matrices are indicated byrectangular boxes. Only 6 of the 9 sub-matrices need to be computed, as3 of the 6 contain redundant information.

Within the sub-matrices, the variables a, b, and c identify the datacorresponding to the antenna elements of the 3-element array. The numberof antenna elements determines the number of sub-matrices within thecovariance matrix. The subscripts 1, 2, and 3 indicate time-domain taps.The number of taps in this example also corresponds to 3, but it will beunderstood that the number of taps can vary in a very broad range and isusually selected according to available processing power. In anotherexample described later in connection with FIG. 5, five such time-domaintaps are used. The number of taps determines the size of a sub-matrix.An asterisk (*) indicates complex conjugation.

Diagonal sub-matrices correspond to the variances of the antennaelements. Non-diagonal sub-matrices correspond to covariance between oneantenna element and another. A first sub-matrix 302 corresponds to thevariance of a first antenna element (a). A second sub-matrix 304corresponds to a covariance of the first antenna element (a) with asecond antenna element (b). A third sub-matrix 306 corresponds to acovariance of the first antenna element (a) with a third antenna element(c).

A fourth sub-matrix 308 corresponds to the covariance of the firstantenna element (a) with the second antenna element (b), which is thecomplex conjugate of the second sub-matrix 304 and does not need to becomputed. A fifth sub-matrix 310 corresponds to the variance of thesecond antenna element (b). A sixth sub-matrix 312 corresponds to thecovariance between the second antenna element (b) and the third antennaelement (c).

A seventh sub-matrix 314 corresponds to the covariance between the firstantenna element (a) and the third antenna element (c), which is thecomplex conjugate the third sub-matrix 306 and does not need to becomputed. An eighth sub-matrix 316 corresponds to the covariance betweenthe second antenna element (b) and the third antenna element (c), whichis the complex conjugate of the sixth sub-matrix 312 and does not needto be computed. A ninth sub-matrix 318 corresponds to the variance ofthe third antenna element.

As illustrated within the sub-matrices that are calculated, eachconventionally calculated sub-matrix in the covariance matrix containsmany complex multiplications. It will be appreciated by one of ordinaryskill in the art that a multiplication of complex numbers in floatingpoint math can be time consuming and can also occupy a relatively largechip area. For example, to calculate a non-diagonal sub-matrix, theconventionally calculated sub-matrix needs 9 complex multiplications inthis 3 tap example. In general, the conventionally calculatednon-diagonal sub-matrix performs n² complex calculations for n number oftaps.

The diagonal sub-matrices 302, 310, 318 can be computed with fewercomplex multiplications. The diagonal sub-matrices correspond tovariance and are Hermitian sub-matrices. Values from below the diagonalof the diagonal sub-matrix need not be computed, but rather, can becopied as complex conjugates from their reflections across the diagonal.For the 3-tap example of FIG. 3, the conventionally calculated diagonalsub-matrix needs 6 complex multiplications.

Redundancy-Induced Reduction in Computational Complexity

FIGS. 4A and 4B illustrate how the number of calculations within thesub-matrices of the covariance matrix can advantageously be reduced innumber. The illustrated embodiment of the covariance matrix againcorresponds to a 3-element antenna array such that covariance matrix has9 sub-matrices, 6 of which are unique. The sub-matrices 402, 404, 406,408, 410, 412, 414, 416, 418 of the covariance matrix of FIG. 4A containapproximately the same data as the sub-matrices 302, 304, 306, 308, 310,312, 314, 316, 318 of the covariance matrix of FIG. 3, but can becomputed in relatively less time by relatively smaller circuitry.

The diagonal sub-matrices, i.e., a first sub-matrix 402, a fifthsub-matrix 410, and a sixth sub-matrix 418 correspond to the variancesof the first antenna element (a), the second antenna element (b), andthe third antenna element (c), respectively. A second sub-matrix 404, athird sub-matrix 406, and a sixth sub-matrix 412 correspond tocovariances between the first antenna element (a) and the second antennaelement (b), the first antenna element (a) and the third antenna element(c), and the second antenna element and the third antenna element (c),respectively. Again, a fourth sub-matrix 408, a seventh sub-matrix 414,and an eighth sub-matrix 416 need not be computed as they are thecomplex conjugates of the second sub-matrix 404, the third sub-matrix406, and the sixth sub-matrix 412, respectively.

Advantageously, rather than computing all of the terms of thenon-diagonal sub-matrices, embodiments copy at least one of the terms ofthe non-diagonal sub-matrix that is conventionally calculated. Oneembodiment of the invention computes only one row and one column of eachnon-diagonal sub-matrix. In the illustrated embodiment of FIG. 4A, thefirst row and the first column are calculated, and the rest of thevalues are copied from the first row and the first column. In anotherembodiment, a different row or a different column can be selected,calculated, and copied. For example, in another embodiment, the last rowand the last column can be selected.

It will be understood by one of ordinary skill in the art that inanother embodiment, a portion of the data that is copied in theillustrated embodiment can also be calculated and still fall within thescope of the invention, i.e., that a term that can be copied iscalculated. In the illustrated embodiment, the terms of the non-diagonalsub-matrix are copied from the calculated first row and the first columnby copying from a term that is to the left and above, i.e., displaced intime by a tap or clock cycle.

The terms can be copied because the terms of the sub-matrix correspondto correlations that are integrated over relatively long intervals, suchas 2 mS. It will be understood that the integration period can vary overa very broad range and that lossy integration techniques can also beused. However, the displacement between terms corresponds to a singletap. In one embodiment, where the sample rate corresponds to 23.516 MHz,the taps are about 42.5 nS apart, which is insignificant relative to theintegration period. Mathematically, the sub-matrices can be consideredto be Toeplitz matrices and advantageously processed with more efficienttechniques than by conventional techniques.

The effect is that the values in a diagonal line from an upper left to alower right are approximately the same in these sub-matrices. Theprocess can repeatedly copy the term through the sub-matrix. Copyingterms in the sub-matrix is described in greater detail later inconnection with FIG. 4B. In the illustrated 3-tap sub-matrix, thenon-diagonal sub-matrix can then be calculated with only 5 complexmultiplications rather than the 9 multiplications required for theconventional calculations. In general, the non-diagonal sub-matrixaccording to one embodiment can be calculated with only 2n−1 complexmultiplications, where n is the number of taps. The number of complexcalculations of one embodiment, 2n−1, can be significantly less than n²complex multiplications, particularly when the number of taps isrelatively large.

The diagonal sub-matrices can be efficiently processed in a similarmanner. One embodiment calculates only one row or only one column of thediagonal sub-matrix. For example, in the illustrated embodiment, onlythe top-most row is calculated, and the remaining values are copied. Inan alternative embodiment, another row, such as the bottom-most row, canbe selected to be computed. In the illustrated embodiment, data valuesare again copied from the value that is to the left and above. Asdescribed earlier, values below the diagonal of a diagonal sub-matrixcan be copied (with appropriate complex conjugation) since thesesub-matrices are Hermitian, and as a result, computation of the diagonalsub-matrix can be accomplished with the complex multiplication of onlyone row or column. For example, for the first sub-matrix 402 of theillustrated embodiment with 3 taps, only 3 complex multiplications areneeded as opposed to the 6 complex multiplications needed for the firstsub-matrix 302 calculated according to conventional techniques.

FIG. 4B illustrates mapping according to an embodiment. The secondsub-matrix 404 of FIG. 4A, which corresponds to the covariance of thefirst antenna element (a) with the second antenna element (b) is used asan example. In the illustrated embodiment, only the first row with theterms a1 b 1*, a1 b 2*, and a1 b 3* and the first column with theadditional terms a2 b 1* and a3 b 1* are calculated with complexmultiplication. The mapping can efficiently fill in the rest of thesecond sub-matrix 404. As illustrated by curved arrows, the terms indiagonals from the upper left to the lower right, i.e., forcorresponding tap number increments between the antenna elements, areapproximately equal and can be copied. As illustrated in FIG. 4B, the a1b 1* term is copied twice along the diagonal. It will be understood thatin embodiments with more taps, the a1 b 1* term can be copied more timesthan shown in FIG. 4B. The a1 b 2* term and the a2 b 1* term are alsocopied. Copying can be performed much more efficiently and with muchless circuitry than floating point multiplication, and the mappingtechnique advantageously saves chip space and processing power.

FIG. 5 illustrates sample data in a covariance matrix. The sample datacorresponds to data that was actually calculated, rather than to datathat was copied via the mapping techniques described earlier inconnection with FIGS. 4A and 4B. The sample data illustrates thevalidity of copying data via the mapping techniques.

An upper table in FIG. 5 corresponds to the taps of an antenna elementcorrelated with itself, i.e., variance. For example, this sample datacorresponds to data that would be found in a diagonal sub-matrix, suchas the diagonal sub-matrices 302, 310, 318, 402, 410, 418, except thatthe data in FIG. 5 corresponds to a five-tap correlator. As shown in theupper table of FIG. 5, the data in diagonals from upper left to lowerright is approximately the same. In addition, the data reflected acrossthe diagonal (from the top-most left to the bottom-most right) is alsoapproximately the complex conjugate. This sample data demonstrates thevalidity of mapping data in diagonal sub-matrices.

A lower table in FIG. 5 corresponds to the taps of one antenna elementcorrelated with another antenna element, i.e., covariance. This sampledata corresponds to data that would be found in a non-diagonalsub-matrix, such as, for example, the second sub-matrix 304 of FIG. 3 orthe second sub-matrix 404 of FIG. 4. As shown in the lower table of FIG.5, the data in diagonals from upper left to lower right is approximatelythe same. This sample data demonstrates the validity of mapping data innon-diagonal sub-matrices.

FIG. 6 illustrates one embodiment of a GPS STAP Filter. The GPS STAPFilter can be implemented in hardware or in a combination of bothhardware and software. A portion of FIG. 6 was described earlier inconnection with FIG. 1D. In one embodiment, the upstream portion of theSTAP filter 118 is implemented in hardware, such as in an FPGA. Otherillustrated components can be implemented in either hardware or insoftware. It will be understood by one of ordinary skill in the art thatin other embodiments, the GPS STAP Filter can be allocated betweenhardware and software in a broad number of variations.

FIG. 6 also illustrates a first zero fill block 620 and a second zerofill block 622, which provide zero padding to the inputs of the inputFFTs. Baseband data from the antenna elements is filled with zeroes suchthat, for example, there can be 8 values of data, then a fill of 8zeroes, then another 8 values of data, and so on. The pattern isindicated as a line for the data and zeroes for the zero fill 624. Thefunction of the zero fill can be implemented in a variety of ways, andin one embodiment, the zero fill is incorporated with the input FFTs asdescribed in greater detail later in connection with FIG. 7. In theillustrated embodiment, the zero fill is provided after the data. Inother embodiments, the zero fill can be provided before the data, orinterspersed within the data. The number of data values between zerofill can vary in a broad range. In FIG. 6, six zeroes are filled at atime. In the example of the FFT with zero fill described in FIG. 8,eight zeroes are filled in at a time.

The illustrated GPS STAP Filter advantageously computes the covariancematrix with FFT Correlation techniques and applies the filtering weightswith FFT convolution techniques. As described earlier in connection withFIG. 1D, the FFT Correlation circuit 128 computes FFT correlation forthe individual antenna elements. A first Inverse FFT (IFFT) processor602 computes the Inverse Fourier Transform of the cross-power spectramaintained in the integration memories of the FFT Correlation circuit128. In one embodiment, a separate IFFT computation is performed foreach of the individual outputs of the cross-power spectra available fromthe FFT Correlation circuit 128.

The number of taps can vary in a very broad range. Where the IFFT iscalculated by a general purpose DSP, the available processing power ofthe DSP can place practical restraints on the number of points of anIFFT that can be computed. In one embodiment, a 64-point IFFT iscomputed for each of the cross-power spectra channels computed. Inanother embodiment, where processing power is relatively scarcer, a16-point IFFT is computed. The first IFFT processor 602 converts thecross-power spectra calculation from frequency domain to time domain.The IFFT can be computed in hardware or in software. For example, thefirst IFFT processor 602 can be implemented in an FPGA with an existingmacro that can be provided by a vendor of the FPGA. In one embodiment,the first IFFT processor 602 is implemented in firmware using asubroutine call from a standardized library.

It will be understood that out of practical considerations, oneembodiment of the GPS STAP filter computes the IFFT by processing thedata in relatively small pieces, performing the IFFT on the relativelysmall pieces, and later recombining the pieces. A variety of techniquescan be used to recombine the pieces. In one embodiment, a Lap and Addtechnique is used to recombine the pieces. One embodiment of the Lap andAdd technique is described in greater detail later in connection withFIG. 8. In another embodiment, a select-save technique is used torecombine the data.

The data is recombined and stored in a correlation memory 604. Thecorrelation memory 604 maintains the cross correlation and autocorrelation functions of the antenna elements. The correlation data ismapped into a covariance matrix as described earlier in connection withFIGS. 2A, 2B, 3, 4A, 4B, and 5. The covariance matrix is inverted by amatrix inversion block 606.

Matrix Inversion Techniques

The matrix inversion block 606 can be implemented in hardware or insoftware. A variety of techniques can be used to invert the covariancematrix in a GPS STAP Filter. Inverting of the covariance matrix is alsoknown as sample matrix inversion or SMI. Although general matrixinverting techniques can be used, the covariance matrix of an adaptivearray or a STAP filter has special matrix properties that canadvantageously permit the computation of the inverse of the covariancematrix in a more efficient manner.

Significantly, the covariance matrix of a STAP filter corresponds to aHermitian matrix. A Hermitian matrix is equal to its conjugatetranspose. One embodiment advantageously permits the computation of theinverse of the covariance matrix by performing triangular UDU^(H) orLDL^(H) factorization, where H indicates the Hermitian transpose, andbackwards or forwards substitution. In one embodiment, the triangularfactorization and the backwards or forwards substitution are functioncalls to subroutines that are provided by a vendor of a DSP chip.

A variety of triangular factorization techniques are applicable. Forexample, Gauss elimination, Bunch-Kaufman decomposition, and Choleskydecomposition techniques can be used. The covariance matrix is positivedefinite for relatively large antenna arrays, such as full-size antennaarrays. However, for small miniature antenna arrays, negativeeigenvalues can be encountered. One embodiment of the STAP filter usesBunch-Kaufman methods to implement the triangular factorization.Bunch-Kaufman methods are about twice as fast as Gauss eliminationtechniques and are compatible with matrices that are positive definite,as well as matrices that are not. In another embodiment, Choleskydecomposition techniques can used in certain situations. AlthoughCholesky decomposition techniques are typically faster and more stablethan Bunch-Kaufman decomposition techniques, Cholesky decompositiontechniques are applicable only to positive definite matrices. In oneembodiment, the decomposition method used is selectable or configurableduring production or by the end-user. In another embodiment, the samplematrix inversion described above is embodied in firmware code that isexecuted by a digital signal processor (DSP), such as a DSP selectedfrom the TMS320 family from Texas Instruments, Inc.

In other embodiments, the inverse of the covariance matrix is computedwith a conventional technique. In one example, a matrix inversionroutine is embodied in firmware code to compute the inverse of thecovariance matrix. The firmware code can be executed by a processor,such as a microprocessor, a digital signal processor, or the like.Hardware circuits can also be configured to perform the sample matrixinversion. In addition, a microprocessor core or a DSP core can also beembedded within an application specific integrated circuit (ASIC).

The outputs of the matrix inversion block 606 are provided as inputs toa multiplier block 608. The multiplier block 608 multiplies the inverseof the covariance matrix from the matrix inversion block 606 with asteering vector 610 to generate weights 612. The weights 612 arecombined with the input samples to reduce or to reject the interferingsignal. Where FFT convolution is not used, the weights can be used ascoefficients in a finite-impulse-response (FIR) filter and applied tothe input samples. In the illustrated GPS STAP filter of FIG. 6, theweights are applied via FFT convolution techniques.

The weights 612 are provided as inputs to FFT processors configured totransform the weights from the multiplier block 608 from time domain tofrequency domain. In the GPS STAP filter shown in FIG. 6, the weights612 are provided to a first weight FFT processor 614 and to a secondweight FFT processor 616. It will be understood that the GPS STAP filtercan be scaled to accommodate a broad number of antenna elements and thatthe number of FFT processors can vary in a broad range. However, thenumber of FFT processors for weight processing should correspond to thenumber of antenna elements. In one embodiment, the FFT processors thattransform the weights are embodiment in software that is executed by aprocessor, such as a DSP.

The transformed weights are provided as inputs to the first multiplier126 and to the second multiplier 160. The first multiplier 126 and thesecond multiplier 160 apply the weights to the input samples.Advantageously, convolution in the frequency domain, as shown in the GPSSTAP filter illustrated in FIG. 6, can be efficiently performed by therelatively simple task of multiplication. It will be recognized by theskilled practitioner that convolution techniques implemented in the timedomain can be significantly more complex to implement. For example,convolution in time domain can be implemented via an FIR filter, but atthe expense of significantly larger chip area and processing power.

The outputs of the various multipliers that perform the convolution inthe frequency domain are provided as inputs to the beamforming summingcircuit 164 such that the space-time filtering of the input samples fromthe individual antenna elements can combined. A dashed block 618indicates where the FFT convolution and the beamforming occur. Theoutput of the beamforming summing circuit 164 is provided as an input tothe IFFT processor 166. The IFFT processor 166 converts the summedconvolutions from frequency domain to time domain. It will be understoodby one of ordinary skill in the art that the IFFT processor 166 can beimplemented in hardware or in software, and can be computed bycomputationally efficient Inverse Fast Fourier Transform techniques orby other Fourier Transform techniques. One embodiment of the IFFTprocessor 166 is described in greater detail later in connection withFIG. 8.

The time-domain output of the IFFT processor 166 is provided as an inputto the Lap and Add circuit 168. The Lap and Add circuit 168 reassemblesthe input samples that were processed by breaking the input samplesequence into relatively small parts (relatively short sequences), eachof which were individually processed. Other techniques, such asselect-save, can also be used to recombine the input sample sequence.One embodiments of the Lap and Add circuit 168 is described later inconnection with FIG. 8. The output of the Lap and Add circuit 168corresponds to the filtered output of the GPS STAP filter, and theoutput is provided as an input to further baseband processing circuits,such as quadrature demodulation circuits, acquisition circuits, and thelike.

Fast Fourier Transform

FIG. 7 illustrates one embodiment of a Fast Fourier Transform (FFT)processor. The illustrated FFT processor can advantageously be used forthe input FFTs, such as the first input FFT processor 120 or the secondinput FFT processor 122 in FIG. 1D and FIG. 6. In one embodiment, theFFT processor can also be used for the weight FFTs, such as the firstweight FFT processor 614 or the second weight FFT processor 616.However, the weight FFTs compute data relatively infrequently and can beimplemented in software. The pipelined FFT processor illustrated in FIG.7 advantageously computes the FFT with 100% efficiency, where efficiencyis defined as the percentage of time at which butterfly elements in theprocessor perform computations. By contrast, one conventional pipelinedFFT processor is only about 50% efficient, see Lawrence R. Rabiner, etal., Theory and Application of Digital Signal Processing, Prentice-Hall1975, pp. 604-609. In the conventional pipelined FFT processor, half ofthe input samples are shifted into an upper data path, and the otherhalf are shifted into a lower data path.

In one embodiment of the GPS STAP filter, half of the input samplesprovided to an FFT processor, such as the first input FFT processor 120,are filled with a value of zero. The value of zero is a constant, andthe FFT processor illustrated in FIG. 7 advantageously directly loadsthis constant and avoids the delay of shifting in a constant.

The FFT processor of FIG. 7 corresponds to a 16-point radix 2 decimationin frequency FFT processor. Although the FFT processor is described in a16-point FFT processor, it will be understood by one of ordinary skillin the art that the number of points of the FFT processor can be variedin a very broad range, such as, for example, 8 points, 64 points, etc.Input samples 702 are advantageously provided directly as inputs to afirst multiplier 704 and to an upper input of a first switch 706. In aconventional FFT processor, the input samples 702 would be provided to aswitch, a delay stage, and a butterfly stage prior to application to thefirst multiplier 704 or to the upper input of the first switch. Thisdirect loading advantageously saves space, saves power, improvesefficiency, and also provides the zero filling.

The input samples 702 can correspond to, for example, the time-domainsamples of the digital baseband signal that corresponds to an antennaelement. The first multiplier 704 performs a complex multiplication ofthe value of the input sample and a first twiddle factor 708. In oneembodiment, the twiddle factors are retrieved from a lookup table. Foran N-point FFT, the twiddle factor is expressed in Equation 2.W _(n) =e ^(−j2πn/N)  (Eq. 2)

In the illustrated FFT processor, the first twiddle factor 708 isapplied to the first multiplier 704 in the following repeating order{W0, W1, W2, W3, W4, W5, W6, W7}. The output of the first multiplier 704is provided as an input to a first delay block 710. The first delayblock 710 delays the output of the first multiplier 704 by four clocksperiods, where a clock period is a step through the pipelined FFT. Thefirst delay block 710 can be implemented by, for example, cascadedregisters in hardware or by retrieving data from memory with an offsetin time. The output of the first delay block 710 is provided as an inputto a lower input of the first switch 706.

The first switch 706 alternately switches between two states with everyfourth clock period. In a first state, the first switch 706 selects thestraight connection, such that the input data on the upper input line iscoupled to an upper output of the first switch 706, and the input dataon the lower input line is coupled to a lower output of the first switch706. In a second state, the first switch 706 selects the crossconnection, such that the input data on the upper input line is coupleto the lower output of the first switch 706, and the input data on thelower input line is coupled to the upper output of the first switch 706.The upper output line of the first switch 706 is provided as an input toa second delay block 712. The delay of the second delay block 712 shouldbe matched to the delay of the first delay block 710, i.e., a four clockcycle delay.

The output of the second delay block 712 and the lower output of thefirst switch 706 are provided as inputs to a first butterfly 714. Anupper output of the first butterfly 714 (on the right) provides the sumof the two inputs on the left. A lower output of the first butterfly 714provides the difference between the two inputs on the left, where thedifference is the value of the upper line minus the value of the lowerline.

The sum output of the first butterfly 714 is provided as an input to anupper input line of a second switch 716. The difference output of thefirst butterfly 714 is provided as an input to a second multiplier 718,which multiplies the difference output with a second twiddle factor 720.The second twiddle factor 720 is provided in the following repeatingsequence: {W0, W2, W4, W6, W0, W2, W4, W6}. The output of the secondmultiplier 718 is provided as an input to a third delay block 722. Thethird delay block 722 delays data in the path by two clock periods. Anoutput of the third delay block 722 is provided as an input to a lowerinput line of the second switch 716.

The second switch 716 is configured to alternately switch between twostates with every other clock period. In the first state, the secondswitch 716 selects the straight connection. In the second state, thesecond switch 716 selects the cross connection. An upper output of thesecond switch 716 is provided as an input to a fourth delay block 724.The delay of the fourth delay block 724 should be matched to the delayof the third delay block 722, i.e., two clock periods.

The output of the third delay block 722 is provided as an input to anupper input line of a second butterfly 726. A lower output of the secondswitch 716 is provided as an input to a lower input line of the secondbutterfly 726.

The second butterfly 726 provides a sum of the inputs on an upper outputline and a difference of the inputs on a lower output line. The polarityof the lower output line is again the upper input line minus the lowerinput line. The sum output of the second butterfly 726 is provided as aninput to an upper input of a third switch 728. The difference output ofthe second butterfly 726 is provided as an input to a third multiplier730.

The third multiplier 730 multiplies the difference output with a thirdtwiddle factor 732. The third twiddle factor 732 is provided in thefollowing repeating sequence: {W0, W4, W0, W4, W0, W4, W0, W4}. Theoutput of the third multiplier 730 is provided as an input to a fifthdelay block 734, which delays the output of the third multiplier 730 byone clock cycle and provides the delayed output as an input to a lowerinput of the third switch 728.

The third switch 728 alternately switches between a first state and asecond state with every clock cycle. In the first state, the thirdswitch 728 selects the straight connection. In a second state, the thirdswitch 728 selects the cross connection. The upper output line of thethird switch 728 is provided as an input to a sixth delay block 736,which should be matched in delay to the delay of the fifth delay block734, i.e., one clock cycle.

The output of the sixth delay block 736 is provided as an input to anupper input of a third butterfly 738. A lower output of the third switch728 is provided as an input to a lower input of the third butterfly 738.The third butterfly 738 provides a sum on an upper output 740 and adifference on a lower output 742. The polarity of the lower output 742corresponds to the upper input minus the lower input. The upper output740 and the lower output 742 of the third butterfly 738 correspond tothe outputs of the FFT processor. The upper output 740 and the loweroutput 742 provide outputs in reverse binary order. In one embodiment,the upper output 740 is provided in the following repeating sequence:{bin₀, bin₄, bin₂, bin₆, bin₁, bin₅, bin₃, bin₇}, and the lower outputis provided in the following repeating sequence: {bin₈, bin₁₂, bin₁₀,bin₁₄, bin₉, bin₁₃, bin₁₁, bin₁₅}. In one embodiment of the GPS STAPfilter, the reverse binary order of the upper output 740 and the loweroutput 742 are maintained in further computations, such as beamforming,to save computations.

Inverse Fast Fourier Transform with Lap and Add

FIG. 8 illustrates one configuration of an Inverse FFT (IFFT) processorwith Lap and Add. The pipelined IFFT processor illustrated in FIG. 8 canbe used in place of the IFFT processor and the Lap and Add circuit 168described earlier in connection with FIGS. 1D and 6. Advantageously, theIFFT processor is also 100% efficient. The IFFT processor illustrated inFIG. 8 corresponds to a 16-point Radix-2 Decimation in Time IFFTprocessor. It will be understood that the data and the operations in theIFFT processor involve complex numbers.

Inputs are applied to the IFFT processor in reverse binary order asdescribed earlier in connection with the reverse binary output of theFFT processor of FIG. 8. Advantageously, the steps of converting tonatural order and to reconvert back to reverse binary order are avoidedby the illustrated FFT and IFFT processor combination. Furtheradvantageously, the output of the IFFT processor of FIG. 8 is in naturalorder.

The reverse binary order inputs from, for example, the beamformingsumming circuit 164 are provided as inputs to a first butterfly 802. Thefirst butterfly 802 provides the sum of the inputs on an upper outputline and a difference of the inputs on a lower output line. Thedifference corresponds to the upper input line minus the lower inputline. The sum output of the first butterfly 802 is provided as an inputto an upper input of a first switch 804. The difference output of thefirst butterfly 802 is provided as an input to a first multiplier 806.

The first switch 804 alternates between a first state and a second stateon every clock cycle. In a first state, the first switch 804 selects thestraight connection and in a second state, the first switch 804 selectsthe cross connection. The first multiplier 806 multiplies the data fromthe difference output with a first twiddle factor 808. The first twiddlefactor 808 is applied in the following repeating sequence: {W0, W4, W2,W6, W1, W5, W3, W7} . The output of the first multiplier 806 is delayedfor one clock cycle by a first delay block 810, and the delayed outputis provided as an input to a lower input of the first switch 804.

The upper output of the first switch is coupled to a second delay block812. The delay of the second delay block 812 should be matched to thedelay of the first delay block 810, i.e., one clock cycle. The output ofthe first delay block 810 is provided as an input to an upper input of asecond butterfly 814. The lower output of the first switch 804 isprovided as an input to a lower input of the second butterfly 814. Thesecond butterfly 814 provides a sum on an upper output line and adifference on a lower output line in a like manner to the firstbutterfly 802.

The sum output of the second butterfly 814 is provided as an input to anupper input line of a second switch 816. The difference output of thesecond butterfly 814 is provided as an input to a second multiplier 818,which multiplies the difference output with a second twiddle factor 820.The second twiddle factor 820 is applied in the following repeatingsequence: {W0, W0, W4, W4, W2, W2, W6, W6}. The output of the secondmultiplier 818 is delayed by a third delay block 822 for two clockcycles, and the delayed output is provided as an input to a lower inputof the second switch 816.

The upper output of the second switch 816 is provided as an input to afourth delay block 824. The delay of the fourth delay block 824 shouldbe matched to the delay of the third delay block 822, i.e., 2 clockcycles. An output of the fourth delay block 824 is provided as an inputto the upper input of a third butterfly 826. A lower output of thesecond switch 816 is provided as an input to a lower input of the thirdbutterfly 826.

The third butterfly 826 provides a sum on an upper output line and adifference on a lower output line as described earlier in connectionwith the first butterfly 802. The sum output of the third butterfly 826is provided as an input to an upper input of a third switch 828. Thedifference output of the third butterfly 826 is provided as an input toa third multiplier 830, which multiplies the difference output with athird twiddle factor 832. The third twiddle factor 832 is applied in thefollowing repeating sequence: {W0, W0, W0, W0, W4, W4, W4, W4}.

The output of the third multiplier 830 is delayed by four clock cyclesby a fifth delay block 834. The delayed output of the fifth delay block834 is provided as an input to a lower input of the third switch 828.The third switch 828 alternately switches between a first state and asecond state with every four clock cycles. In the first state, the thirdswitch 828 selects a straight connection. In the second state, the thirdswitch 828 selects a cross connection. An upper output of the thirdswitch 828 is coupled to a sixth delay block 836. The delay of the sixthdelay block 836 is matched to the delay of the fifth delay block 834,i.e., four clock cycles. The output of the sixth delay block 836 isprovided as an input to an upper input of a fourth butterfly 838. Alower output of the third switch 828 is provided as an input to a lowerinput of the fourth butterfly 838.

The fourth butterfly 838 provides a sum on an upper output line and adifference on a lower output line. The polarity of the differencecorresponds to the difference between the upper input line and the lowerinput line. The sum from the fourth butterfly 838 is provided as aninput to a summer 840. The summer 840 performs the lap and add bysumming the sum output of the upper output of the fourth butterfly 838with an output of a seventh delay block 842. The seventh delay block 842delays the difference output of the fourth butterfly 838 by 8 clockcycles. The output of the summer 840 is provided as an output of theIFFT with lap and add. In one embodiment, the output of the summer 840is provided as an input to additional baseband processing circuits, suchas circuits for quadrature demodulation and/or circuits for acquisition.

Phase Compensation Injection

Embodiments can advantageously filter interfering signals from a varietyof sources, including jammers. However, a GPS receiver can be exposed toa relatively rapidly changing jamming field. Although embodiments canfilter out these jamming fields, the GPS STAP filtering can also inducerelatively rapid phase changes to the baseband signal.

The rapidly changing phase can cause a GPS receiver to lose carrierphase lock in a carrier tracking loop. Typically, the carrierphase-locked-loop has a relatively narrow bandwidth because of the lowsignal strength of a GPS signal due to the relatively great distancebetween a GPS receiver and a GPS space vehicle. A phase locked loop withnarrow bandwidth is typically unable to track rapidly changing phases.

One embodiment calculates the phase changes induced by application ofthe adaptive weights and accordingly steers the carrier tracking loopwith the phase changes induced by the GPS STAP filter such that thecarrier tracking loop can maintain phase lock with the GPS signal. Thiscan be performed in a manner analogous to that used by inertialmeasurement units (IMUs) in high dynamic environments.

Various embodiments of the invention have been described above. Althoughthis invention has been described with reference to these specificembodiments, the descriptions are intended to be illustrative of theinvention and are not intended to be limiting. Various modifications andapplications may occur to those skilled in the art without departingfrom the true spirit and scope of the invention as defined in theappended claims.

1. A method of reusing data in a GPS space-time adaptive processing(STAP) filter, the method comprising: calculating Fourier Transforms ofinput samples for GPS antenna elements; using the calculated FourierTransforms to compute Fourier Transform correlation at least forcomputation of cross-power spectra among the GPS antenna elements; andreusing the same calculated Fourier Transforms to compute FourierTransform convolution for beamforming.
 2. The method as defined in claim1, wherein calculating Fourier Transforms comprises calculating FastFourier Transforms.
 3. The method as defined in claim 1, wherein theantenna element is a GPS antenna element, the cross-power spectra is forat least the GPS antenna element, and the beamforming is for the GPSantenna element.
 4. An apparatus comprising: Fourier Transformprocessors configured to compute Fourier Transforms of data samples fromtwo or more antennas; a beamformer coupled to outputs of the FourierTransform processors, wherein the beamformer computes convolution withthe Fourier Transforms of the data samples; and a correlation circuit incommunication with the outputs of the same Fourier Transform processors,wherein the correlation circuit is configured to compute correlationamong the two or more antennas at least for computation of cross-powerspectra with the same Fourier Transforms of the data samples.
 5. Theapparatus as defined in claim 4, wherein the Fourier Transform processorcomprises a Fast Fourier Transform processor.
 6. The apparatus asdefined in claim 4, wherein the apparatus further comprises a globalpositioning system (GPS) receiver.
 7. The apparatus as defined in claim4, wherein the data samples are from GPS antennas, and the computedcorrelation is of the GPS antennas.
 8. A method of computing a FastFourier Transform (FFT), the method comprising: receiving input samplesin natural order; providing the input samples directly to an FFTpipeline without a delay stage that implements filling of a constant,wherein the direct loading to the FFT pipeline includes the constantloading; and processing the input samples through the FFT pipeline. 9.The method as defined in claim 8, wherein the constant is zero.
 10. Themethod as defined in claim 8, wherein the input samples are provideddirectly to the multiplier and to the switch of an FFT pipeline withouta delay stage that implements filling of a constant.
 11. The method asdefined in claim 8, wherein the FFT pipeline is configured to compute anFFT with decimation in frequency.
 12. A pipelined circuit forcomputation of a Fourier Transform, the pipelined circuit comprising: amultiplier with an input coupled to an input terminal, wherein themultiplier is configured to multiply input samples with twiddle factors;a first delay stage with an input coupled to an output of themultiplier; a switch having a first input coupled to the input terminaland a second input coupled to an output of the first delay stage,wherein the switch is configured to provide a straight connection in afirst state and a cross connection in a second state; a second delaystage with an input coupled to a first output of the switch; and abutterfly stage with a first input coupled to a second output of theswitch and a second input coupled to an output of the second delaystage, wherein the butterfly stage is configured to couple to anotherstage of the pipelined circuit for processing of the Fourier Transform.13. The pipelined circuit as defined in claim 6, further comprising asecond stage, wherein the second stage comprises: a second multiplierwith an input coupled to a difference output of the butterfly stage,wherein the second multiplier is configured to multiply data from thedifference output with twiddle factors; a third delay stage with aninput coupled to an output of the second multiplier; a second switchwith a first input coupled to a sum output of the butterfly stage and asecond input coupled to an output of the third delay stage, wherein thesecond switch is configured to provide a straight connection in a firststate and a cross connection in a second state; a fourth delay stagewith an input coupled to a first output of the second switch; and asecond butterfly stage with a first input coupled to a second output ofthe second switch and a second input coupled to an output of the fourthdelay stage, wherein outputs of the second butterfly stage are providedto a subsequent stage for further processing of the Fourier Transform.14. The pipelined circuit as defined in claim 6, wherein the pipelinedcircuit is embodied in a GPS receiver.